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INTEGRATED CIRCUITS
DATA SHEET
SAA7367 Bitstream conversion ADC for digital audio systems
Product specification Supersedes data of 1996 Jun 17 File under Integrated Circuits, IC01 1998 Nov 17
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
FEATURES * Total Harmonic Distortion plus Noise (THD + N) = -88 dB (0.004%); DR = 93 dB; S/N = 97 dB * Simple interfacing to analog inputs * Small, non-critical PCB layout * Low pin-out SO24 package (pin-compatible to SAA7366) * 4 flexible serial interface modes * 4.5 to 5.5 V operation * Standby mode * Detection of digital signal -1 dB amplitude * Up to 18 significant bits serial output * Selectable high-pass filter. APPLICATIONS The device is designed for the digital acquisition of analog audio signals for digital audio systems such as: * Compact Disc-Recordable (CD-R) * Audio digital signal processing systems for hi-fi and musical instrument applications * Digital Audio Tape (DAT). QUICK REFERENCE DATA SYMBOL VDDD IDDD VDDA IDDA fBCK fs THD + N DR S/N PARAMETER digital supply voltage digital supply current analog supply voltage analog supply current clock input frequency sample rate total harmonic distortion plus noise dynamic range signal-to-noise ratio at 0 dB input at -60 dB CONDITIONS - 4.5 - 4.60 18 - 90 - MIN. 4.5 17 5.0 13 12.288 48 -88 93 97 TYP. 5.0 - 5.5 - 12.8 50 -80 - - GENERAL DESCRIPTION
SAA7367
The SAA7367 is a CMOS low-cost stereo Analog-to-Digital Converter (ADC) using the Philips bitstream conversion technique.
MAX. 5.5 V
UNIT mA V mA MHz kHz dB dB dB
ORDERING INFORMATION TYPE NUMBER SAA7367 PACKAGE NAME SO24 DESCRIPTION plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT137-1
1998 Nov 17
2
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
BLOCK DIAGRAM
SAA7367
handbook, full pagewidth
VSSA 13 operational amplifier 16 17 operational amplifier
VrefR 15
TESTB 12
STDB 2
BIR BOR
REFERENCE VOLTAGE GENERATOR
CLOCK GENERATION AND CONTROL
4
CKIN
VDACP
19 SIGMADELTA MODULATOR TIMING GENERATOR SIGMADELTA MODULATOR DECIMATION FILTER STAGE 2 STAGE 1 3 HALF-BAND COMB FILTERS FILTER
5 6
VDDD VSSD
Iref
14
REFERENCE CURRENT GENERATOR
VDACN
18
SAA7367
HIGH-PASS FILTER 20 21 REFERENCE VOLTAGE GENERATOR operational amplifier 22 VrefL 11 10 24 1 SFOR
MGE645
BOL BIL
3 7 SERIAL OUTPUT INTERFACE 8 9
OVLD SDO SWS SCK
operational amplifier 23 VDDA
HPEN TEST1
SLAVE
Fig.1 Block diagram.
1998 Nov 17
3
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
PINNING SYMBOL SFOR PIN 1 DESCRIPTION
SAA7367
TTL level input; in normal mode this input selects the serial interface output format; output format is selected as follows: SFOR = HIGH selects Format 1 SFOR = LOW selects Format 2 (similar to I2S)
STDB
2
schmitt-trigger input; in normal mode, this input is used to select standby mode: STDB = HIGH selects normal operation STDB = LOW selects standby mode (low power consumption)
OVLD
3
TTL level output; in normal mode this output indicates whether the internal digital signal is within 1 dB of maximum; if so, the output will go HIGH for 131072 clock cycles (approximately 11 ms); in standby mode this output is forced LOW CMOS level input; system clock input; nominally clocked at 256fs digital supply voltage (4.5 to 5.5 V) digital ground TTL level output (3-state); in normal mode this pin outputs data from the serial interface; in standby mode, this output is high impedance TTL level input/output; serial interface word select signal; in master mode (SLAVE = LOW), this pin outputs the serial interface word select signal; in slave mode (SLAVE = HIGH), this pin is the word select input to the serial interface; in standby mode (STDB = LOW) this pin is always an input (high impedance); for polarity: see Table 1 TTL level input/output; in master mode (SLAVE = LOW) the pin outputs the serial interface bit clock; in slave mode (SLAVE = HIGH) this pin is the input for the external bit clock; data on SDO is clocked out on the HIGH-to-LOW transition of SCK; the data is valid on the LOW-to-HIGH transition Test 1; TTL level input with internal pull-down; in slave mode (slave = HIGH), this pin is used to select extra serial interface formats (see Table 2) TTL level input; this input is used to enable the internal high-pass filter when HIGH; in scan-test mode (TESTB = LOW and TEST1 = LOW) this pin functions as `scan chain c' input Test B; CMOS level input with internal pull-up; in normal applications, this input should be left HIGH analog ground; this pin is internally connected to VSS via the on-chip substrate contacts current reference generator output; 33 k in parallel with 22 nF is connected from this pin to VSSA right channel analog reference output voltage (12VDDA) buffer operational amplifier inverting input for right channel buffer operational amplifier output for right channel negative 1-bit DAC reference voltage input, connected to 0 V positive 1-bit DAC reference voltage input, connected to +5 V buffer operational amplifier output for left channel buffer operational amplifier inverting input for left channel left channel analog reference output voltage (12VDDA) analog supply voltage (4.5 to 5.5 V)
CKIN VDDD VSSD SDO SWS
4 5 6 7 8
SCK
9
TEST1 HPEN TESTB VSSA Iref VrefR BIR BOR VDACN VDACP BOL BIL VrefL VDDA
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1998 Nov 17
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Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
SYMBOL SLAVE PIN 24 SLAVE = HIGH selects slave mode SLAVE = LOW selects master mode Table 1 SWS polarity CONDITIONS DESCRIPTION TTL level input; used to select the serial interface operating mode:
SAA7367
POLARITY SLAVE AND TEST1 SLAVE = LOW or TEST1 = LOW SLAVE = HIGH and TEST1 = HIGH SWS LOW LOW LOW LOW Table 2 Selection of serial interface formats via TEST1 CONDITIONS SELECTED FORMAT SFOR HIGH LOW TEST1 LOW HIGH LOW HIGH FUNCTIONAL DESCRIPTION
handbook, halfpage
SFOR LOW HIGH LOW HIGH left data right data right data left data
format 1 format 3 format 2 format 4
General
SFOR STDB OVLD CKIN VDDD VSSD SDO SWS SCK 1 2 3 4 5 6 24 SLAVE 23 VDDA 22 VrefL 21 BIL 20 BOL 19 VDACP 18 VDACN 17 BOR 16 BIR 15 14 13
MGE644
SAA7367
7 8 9
TEST1 10 HPEN 11 TESTB 12
VrefR Iref VSSA
The SAA7367 is a bitstream conversion CMOS ADC for digital audio systems. The conversion is achieved using a third-order Sigma-Delta Modulator (SDM), running at 128 times the output sample frequency (fs). The high oversampling ratio greatly simplifies the design of the analog input anti-alias filter. In most events, the internal buffer operational amplifier, configured as a low-pass filter, will suffice. The 1-bit code from the SDM is filtered and down-sampled (decimated) to 1fs by Finite Impulse Response (FIR) filters. An optional I2R high-pass filter is provided to remove DC, if required. The device has been designed with ease of use, low board area and low application costs in mind. Clock frequency The external clock input on pin CKIN runs at 256fs, which can range from 18 to 50 kHz.
Fig.2 Pin configuration.
1998 Nov 17
5
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
Input buffer Two input buffers are provided, one for each channel, for signal amplitude matching, signal buffering and anti-alias filter purposes. These are configured for inverting use. Access is provided by pins BIL, BIR (inverting inputs) and BOL, BOR (outputs), for left and right channels respectively. By the choice of feedback component values, the application signal amplitude can be matched to the requirements of the ADC. Typically, the operational amplifiers are configured as low-pass filters with a gain of 1 and a pole at approximately 5fs. Remark: the complete ADC is non-inverting. Hence, a positive DC input (referenced to Vref) will yield a positive digital output. Input level The overall system gain is proportional VDDA, or more accurately the potential difference between the DAC reference voltages (VVDACP) and (VVDACN). For convenience, the ADC input signal amplitude is defined as that amplitude seen on BOL or BOR, the operational amplifier outputs (i.e. the input to the SDM). Also, the 0 dB input level is defined as that which gives a -1 dB (actually -1.12 dB) digital output, relative to full-scale swing. This reduced gain provides headroom to accommodate small random DC offsets, without causing the digital output to clip. Hence: ( V VDACP - V VDACN ) V I ( 0 dB ) = -----------------------------------------------------5 V (RMS) The user of the IC should ensure that, when all sources of signal amplitude variation are taken into account, the maximum input signal should conform to the 0 dB level. In the event that the maximum signal level cannot be pre-determined, e.g. live microphone input, the average signal level should be set at -10 to -20 dB down. The exact value will depend on the application and the balance between headroom and operating Signal-to-Noise Ratio (SNR). Behaviour during overload As previously defined, the maximum input level for normal operation is 0 dB. If the input level exceeds this value, clipping may occur. Within the system, excessive amplitudes are detected after the high-pass filter. Infringements are limited to the maximum permitted positive or negative values 217 - 1 or -217 respectively. 1998 Nov 17 6
SAA7367
Input signals in the range 0 to 1 dB may or may not be clipped, depending on the values of DC dither and small random offsets in the analog circuitry. When using the recommended application circuitry, clipping will initially be observed on negative peaks, due to the use of negative DC dither. The maximum level of overload that can be safely tolerated is application circuit dependent. In the case of the recommended circuit, the following applies: the inverting operational amplifier inputs BIL and BIR are protected from excessive voltages (currents) by diodes to VDDA and VSSA. These have absolute maximum ratings of Id = 20 mA, with a safe practical limit of 2 mA. Given the input resistor of 10 k, 2 mA diode current and the operation of the operational amplifier, a maximum signal (applied to the input resistor) of 30 V can be handled safely. This level represents an overload of 26 dB. During overload, the in-band portion of the waveform will be correctly converted. The out-of-band portion will be limited as previously detailed. Sigma-Delta Modulator (SDM) The SAA7367 uses two third-order SDMs with a quantization noise floor of approximately -104 dB. The scaling of the feedback has been optimized for stable operation, even during overload. Thus, with a maximum signal swing of 0 V to VDDA on the input, the digital output remains well-behaved, i.e. it does not burst into random oscillation. During overload, the output is simply a clipped version of the input. The gain of this stage is -4.64 dB. Decimation filter Decimation from 128fs is performed in two stages. The first stage, a comb filter, uses 64 symmetrical coefficients to implement a 3rd sin xx characteristic. This filter decimates from 128 to 8fs. The second stage, an FIR filter, consists of three half-band filters, each decimating by a factor of 2. The overall characteristics are given in Table 3.
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
Table 3 Overall filter characteristics ITEM Pass band ripple Stop band Dynamic range Gain High-pass filter An optional I2R high-pass filter is provided to remove unwanted DC components. The operation is selected when HPEN is HIGH and deselected when LOW. The filter has the characteristics given in Table 4. Table 4 High-pass filter characteristics ITEM Pass band ripple Pass band gain Droop Attenuation at DC Dynamic range Serial interface The serial interface provides 2 formats in master mode and 4 in slave mode (see Figs 3 and 4). Format 2 is similar to Philips I2S. In all modes, the interface provides up to 18 significant bits of output data per channel. During standby mode (STDB = LOW), all interface pins are in their high impedance state. On recovery from standby, the serial data output SDO is held LOW until valid data is available from the decimation filter. This time depends on whether the high-pass filter is selected: HPEN = 0; T = 1024/fs, T = 21.3 ms when fs = 48 kHz HPEN = 1; T = 12288/fs, T = 256.0 ms when fs = 48 kHz Overload detection The OVLD output is used to indicate when the output data, in either the left or right channel, is greater than -1 dB (actual figure -1.023 dB) of the maximum possible digital swing. When this condition is detected, the OVLD output is forced HIGH for at least 512fs cycles (10.6 ms at fs = 48 kHz). This time-out is reset for each infringement. at 0.00042fs at 0.00000036fs 0 to 0.45fs CONDITION VALUE (dB) none 0 0.146 >40 >110 CONDITION 0 to 0.45fs 0.45 to 0.47fs >0.55fs 0 to 0.42fs DC VALUE (dB) 0.1 -0.5 -60 110 3.52 Standby mode
SAA7367
The STDB pin activates a power saving mode when the device function is not required. This pin can also be used as a chip enable. On a HIGH-to-LOW transition of the STDB pin, the internal control circuitry starts a timed power-down sequence. This takes approximately 32 system clock cycles to complete. Transitions on STDB that are shorter than 32 clock cycles may have an indeterminate effect. However, the device will always recover correctly. During standby, the following occurs: * The internal logic clock is disabled * The serial interface pins are forced to high impedance * The OVLD output is forced LOW * The analog circuitry is disabled * The nominal external analog node voltages are maintained by a low-power circuit. This feature ensures a fast recovery from standby mode. Note: since the serial interface pins are high impedance during standby, these pins could be wire-ORed with other serial interface ICs. On a LOW-to-HIGH transition, the device reverts back to normal operation. This process takes approximately 256 system clock cycles. Before SDO is enabled, the output data is forced LOW. SDO remains LOW until good data is available from the decimation filter (see Section "Serial interface"). The STDB pin has a Schmitt-trigger input. A simple power-on-reset function can be effected using an external capacitor to VSS and resistor to VDD. TEST1 This pin is used to select the serial interface format in slave mode.
1998 Nov 17
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Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA VI IIK VO IO IDD(tot) ISStot Tamb Tstg Note 1. VSSD and VSSA must be connected to a common potential. QUALITY SPECIFICATION DC input voltage DC input clamp diode current DC output voltage DC output source or sink current total DC supply current total DC supply current operating ambient temperature storage temperature PARAMETER analog supply voltage (note 1) MIN. -0.5 -0.5 - -0.5 - - - -40 -65
SAA7367
MAX. +6.5 +6.5 20 VDD + 0.5 20 0.5 0.5 +85 +150 V V
UNIT
mA V mA A A C C
In accordance with "SNW-FQ-611-E". The number of the quality specification can be found in the "Quality Reference Handbook". CHARACTERISTICS VDDD = 4.5 to 5.5 V; VDDA = 4.5 to 5.5 V; fs = 18 to 50 kHz; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDDD IDDD VDDA IDDA Ptot Istb Pstb digital supply voltage digital supply current analog supply voltage analog supply current total power dissipation standby supply current standby power consumption fs = 48 kHz fs = 48 kHz 4.5 - 4.5 - - - - 5 17 5 13 150 160 800 5.5 - 5.5 - - - - V mA V mA mW A W PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital part: inputs SFOR, SLAVE AND HPEN VIL VIH ILI Ci LOW level input voltage HIGH level input voltage input leakage current input capacitance -0.5 2.0 -10 - - - - - +0.8 VDD + 0.5 +10 10 V V A pF
1998 Nov 17
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Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
SYMBOL CKIN VIL VIH ILI Ci TEST1 VIL VIH Ri Ci TESTB VIH Ri VIL VIH Vhys ILI Ci HIGH level input voltage internal resistance to VDD LOW level input voltage HIGH level input voltage hysteresis voltage input leakage current input capacitance 0.7VDD - -0.5 0.6VDD 200 -10 - - 50 - - - - - LOW level input voltage HIGH level input voltage internal resistance to VSS input capacitance -0.5 2.0 - - - - 50 - +0.8 LOW level input voltage HIGH level input voltage input leakage current input capacitance -0.5 0.7VDD -10 - - - - - PARAMETER CONDITIONS MIN. TYP.
SAA7367
MAX.
UNIT
0.3VDD VDD + 0.5 +10 10
V V A pF
V V k pF
VDD + 0.5 - 10
VDD + 0.5 - 0.4VDD VDD + 0.5 - +10 10
V k
STDB (SCHMITT TRIGGER) V V mV A pF
Digital part: inputs/outputs SWS AND SCK VIL VIH ILl Ci VOL VOH CL LOW level input voltage HIGH level input voltage 3-state leakage current input capacitance LOW level output voltage HIGH level output voltage output load capacitance IO = -400 A IO = 20 A note 1 -0.5 2.0 -10 - - 2.4 - - - - - - - +0.8 VDD + 0.5 +10 10 0.4 - 50 V V A pF V V pF
Digital part: outputs OVLD VOL VOH CL SDO VOL VOH ILI CL LOW level output voltage HIGH level output voltage 3-state leakage current output load capacitance note 1 IO = -400 A IO = 20 A - 2.4 -10 - - - - - 0.4 - +10 50 V V A pF LOW level output voltage HIGH level output voltage output load capacitance IO = -400 A IO = 20 A note 1 - 2.4 - - - - 0.4 - 50 V V pF
1998 Nov 17
9
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
SYMBOL Digital part: timings CKIN tr tf fi msr input rise time input fall time input frequency mark-to-space ratio fs > 32 kHz fs 32 kHz Serial Interface master and slave modes (see Figs 5 and 6) SCK tr tf tL tH fclk tidle SWS tr tf tL tH fS td tsu SDO th tsu tr tf data output hold time data output set-up time data output rise time data output fall time CL = 50 pF; note 1 CL = 50 pF; note 1 100 50 - - - - - - - - 50 50 rise time fall time LOW time HIGH time frequency delay from SCK set-up time to SCK master mode slave mode slave mode CL = 50 pF; note 1 CL = 50 pF; note 1 T = 1/fs T = 1/fs - - 0.05T 0.05T 1fs -50 50 150 - - 0.5T 0.5T 1fs - - - - 50 50 rise time fall time LOW time HIGH time clock frequency burst clock idle time CL = 50 pF; note 1 CL = 50 pF; note 1 T = 164fs T=
1 64fs
SAA7367
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
- - 4.60 40 30
- - - - -
10 10 12.8 60 70
ns ns MHz % %
- - 0.4T 0.4T 64fs - 0
- - - - 64fs - -
50 50 0.6T 0.6T 64fs 64fs 0.5T
ns ns ns ns MHz MHz ns
master mode slave mode slave mode; T = 1/fs
ns ns ns ns MHz ns ns ns
0.95T 0.95T 1fs +50
ns ns ns ns
1998 Nov 17
10
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7367
MAX.
UNIT
Analog part at: VDD = VDDA = 5 V; Tamb = 25 C VrefL AND VrefR VO RDC output voltage DC impedance normal mode standby mode CURRENT REFERENCE: Iref VO IO VDACN VI VDACP VI VI(off) RL ZO THD + N input voltage - - decoupled to Vref - - f = 0 to 20 kHz - VDDA <10 10 100 -87 - - - - - V BUFFER OPERATIONAL AMPLIFIERS: BIL, BOL, BIR AND BOR input offset voltage load resistance; (drive capability) output impedance total harmonic distortion plus noise mV k dB input voltage - VSS - V out put voltage output current R = 33 k - - 0.5VDDA 76 - - V A 0.475VDDA - - 0.5VDDA 1.3 100 0.525VDDA - - V k k
OVERALL PERFORMANCE (ANALOG IN, DIGITAL OUT) tgd sb DR THD + N S/N cs G Notes 1. Load capacitance is valid for master mode only. 2. See also Section "Input level" of Chapter "Functional description"; valid for left or right channel. group delay time stop band attenuation dynamic range total harmonic distortion plus noise signal-to-noise ratio channel separation gain note 2 T = 1/fs f > 0.546 fs 0 to 20 kHz 0 to 20 kHz A-weighted - 60 90 - - - -1.4 25T - 93 -88 97 92 -1 - - - -80 - - -0.8 s dB dB dB dB dB dB
1998 Nov 17
11
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
SAA7367
handbook, full pagewidth
1 STEREO WORD LEFT DATA
FORMAT 2
RIGHT DATA
FORMAT 1 18 CLOCKS SCK
RIGHT DATA 14 CLOCKS 18 CLOCKS
LEFT DATA 14 CLOCKS
SDO
MSB
LSB
MSB
LSB
MSB
MGE647
Fig.3 Serial interface master mode format.
1998 Nov 17
12
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
SAA7367
handbook, full pagewidth
1 STEREO WORD LEFT DATA RIGHT DATA
FORMAT 2
FORMAT 4 idle SCK
LEFT DATA N CLOCKS
RIGHT DATA N CLOCKS
SDO
MSB
LSB
MSB
LSB
MSB
1 STEREO WORD FORMAT 1 RIGHT DATA LEFT DATA
FORMAT 3 idle SCK
RIGHT DATA N CLOCKS
LEFT DATA N CLOCKS
SDO
MSB
LSB
MSB
LSB
MSB
MGE648
Fig.4 Serial interface slave mode format.
1998 Nov 17
13
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
SAA7367
handbook, full pagewidth
tr 2.0 V
tf
tL
tH
SCK 0.8 V td 2.0 V SWS 0.8 V tr 2.0 V SDO VALID 0.8 V
MGE649
tsu
th
tf
MSB FORMAT 1
MSB FORMAT 2
Fig.5 Serial interface master mode timing.
handbook, full pagewidth
tr 2.0 V
tf
tL
tH
SCK 0.8 V td 2.0 V SWS 0.8 V tr 2.0 V SDO VALID 0.8 V
MGE650
tsu
tsu
th
tf
MSB FORMAT 1
MSB FORMAT 2
Fig.6 Serial interface slave mode timing.
1998 Nov 17
14
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handbook, full pagewidth
APPLICATION INFORMATION
Philips Semiconductors
Bitstream conversion ADC for digital audio systems
left channel input 100 k 47 F 47 F 47 nF
(1)
right channel input 100 k +5 V 47 F 10 k 270 270 Rdither 330 k 47 F 47 nF BOL 20
(1)
(1)
10 k Rdither
47 nF
47 F
+5 V
4.7 47 F 47 nF
(1)
620 k 10 k 68 pF
33 k
10 k 68 pF VDACN 18 BOR 17 16 BIR VrefR 15 14 22 nF Iref VSSA 13
VDDD or VSSD SLAVE 24 VDDA 23 VrefL 22
BIL 21
VDACP 19
15
1 SFOR VDDD or VSSD from microcontroller power-down control to microcontroller overload detection system clock input 47 nF
(1)
SAA7367
2 STDB 3 OVLD 4 CKIN 5 VDDD 6 VSSD 7 SDO 8 SWS 9 SCK 10 TEST1 11 HPEN 12 TESTB
VDDD or VSSD
MGE646
47 F 4.7 +5 V
to serial interface receiver circuit
Product specification
SAA7367
(1) These capacitors should preferably be surface-mounted components located as close as possible to the device pins.
Fig.7 Application circuit.
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
PACKAGE OUTLINE SO24: plastic small outline package; 24 leads; body width 7.5 mm
SAA7367
SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1998 Nov 17
16
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
SAA7367
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Nov 17
17
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE HLQFP, HSQFP, HSOP, SMS PLCC(3), SQFP SSOP, TSSOP, VSO Notes SO LQFP, QFP, TQFP not suitable(2) suitable not not recommended(3)(4) recommended(5) not suitable suitable suitable suitable suitable suitable
SAA7367
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1998 Nov 17
18
Philips Semiconductors
Product specification
Bitstream conversion ADC for digital audio systems
NOTES
SAA7367
1998 Nov 17
19
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/00/02/pp20
Date of release: 1998 Nov 17
Document order number:
9397 750 04775

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